The current 3D packaging and interconnection technology is generally limited to the tasks of producing the dense arrays of stacked memory or processing IC chips for the sake of increasing the capacity and processing power within the limited footprint on the printed circuit board. The current technological processes utilize the soldering connections of the pre-aligned arrays of the designated contact pads by dipping the edge of the stack into a vat of molten solder or by re-flowing the toughing solder bumps on the adjacent chips. What is needed is a method for the fabrication of 3D circuits which overcomes problems in the art.